As GHz band high frequency devices represented by an amplifying element for transmitting and receiving in the satellite broadcasting, there have widely been known, for instance, GaAs-MESFET (Metal Semiconductor FET) whose channel layer is a GaAs epitaxial layer deposited on a GaAs substrate, and FETs which make use of a two-dimensional electron layer accumulated in the interface of the hetero structure of GaAs and AlGaAs, i.e., so-called HEMT's (High Electron Mobility Transistors; Japanese Patent Application Laying-open No. 94780/1981). The GaAs device operates at a high speed for the reason that the electron mobility of GaAs is high on the order of about 8,000 cm.sup.2 /V. sec in its undoped state (intrinsic state), which is several times (5 to 6 times) greater than that of Si.
However, the channel layer of a GaAs-MESFET must be doped with impurities, and accordingly the electron mobility thereof is reduced to about 4,000 cm.sup.2 /V. sec owing to the scattering of conduction electrons by the impurities. To solve this problem, the GaAs-HEMT is designed to have a structure in which an electron donor layer doped with impurities and a channel layer are separated from one another through a heterojunction of different semiconductors having different bandgaps, whereby the scattering effect due to the impurities is reduced and a high electron mobility is established.
GaAs-HEMT's in which the relation between the impurity concentration and the film thickness of the electron donor layer thereof is specified are, for instance, disclosed in Japanese Patent Application Laying-open No. 53714/1984, U.S. Pat. No. 4,424,525 and U.S. Pat. No. Re. 33,584.
In the HEMT structure, it is difficult to form an ohmic electrode and to control the electron mobility since the impurity concentration in the channel layer is in general low. There has been proposed, in Japanese Patent Application Laying-open No. 54673/1986, a GaAs-FET in which both electron donor and channel layers forming a heterojunction are doped with impurities for the purpose of compensating the foregoing drawback.
In addition, Japanese Patent Application Laying-open No. 276267/1986 proposes a GaAs semiconductor heterojunction device whose region doped with impurities spreads into the region including a heterojunction in order to increase the concentration of two-dimensional electron gas.
Further, Japanese Patent Application Laying-open No. 131565/1986 proposes a double heterojunction GaAs-FET in which both upper and lower surfaces of an n-type channel layer make contact with electron donor layers of a compound semiconductor doped with impuritiers, which electron donor layers have energy bandgaps layer than that of the channel layer.
U.S. Pat. No. 4,424,525 proposes a GaAs-FET which makes use of the heterojunction and in which both electron donor and channel layers positioned below the source and drain of the GaAs-FET, respectively, are doped with impurities.
However, an FET having a very short gate length equal to or less than 0.2 .mu.m is required for producing devices, from the above-mentioned devices, capable of transmitting and receiving radio waves of several tens of GHz region. Such a short gate electrode might sometimes be formed by the photolithography technique, but generally, the formation thereof requires an advanced technology, and stable production thereof is quite difficult.
Although the electron beam lithography has widely been adopted in practice, it is inferior to the photolighography technique from the viewpoint of industrial mass-productivity. Moreover, the gate length must be made more finer in order to produce high frequency devices capable of operating at a higher frequency region from the aforementioned GaAs-FETs such as GaAs-MESFETs and GaAs-HEMTs. However, if the gate length is made precise to obtain devices capable of operating at a higher frequency, the development of novel techniques and advanced processing techniques which are industrially impracticable are required. For this reason, the development of high frequency devices has been desired having novel structures which can be easily made precisely, mass-produced, and can cope with higher frequency bands as compared with those of the conventional devices.
Under such circumstances, Japanese Patent Application Laying-open No. 272080/1988 proposes the use of a thin film of InGaAs which has an electron mobility higher than that of GaAs as the channel layer for FETs. In the structure according to this proposal, a double heterojunction is formed by sandwiching the n-type InGaAs layer serving as a channel layer by different GaAs layers. This patent application discloses trial production examples in which both of these GaAs layers are doped and both of these layers are not doped. A GaAs plate is used as a substrate. In this proposal, the InGaAs layer directly comes in contact with the GaAs layers and, therefore, the atomic ratio of In content to As content in the InGaAs layer should be small in order to satisfy the requirement of lattice matching. The ratio should be limited within 20% in the examples of the foregoing proposal and the thickness of the InGaAs layer should also be thin on the order of 150 .ANG.. If the rate of In is low as in the foregoing case, the mobility is not substantially improved as compared with GaAs.
Moreover, there have been studied FETs whose channel layer comprises a high-quality thin film of InAs having an electron mobility and a saturation speed overwhelmingly higher than those of GaAs.
The high electron mobility and saturation speed of InAs may allow for even FETs having a gate length longer than that of the GaAs-FET to transmit and receive high frequency radio waves to the same degree as the GaAs-FETs. However, these conventional attempts to develop InAs-FETs suffer from the following problems:
(1) Substrates to be used are expensive and thus are not suitable for use as industrial materials. PA1 (2) The structure thereof is very complicated and problems relating to reliability and manufacturing processes arise. PA1 (3) Such devices are liable to cause deffects due to the difference in lattice constant between the InAs layer and a semiconductor layer which comes in contact with the former. PA1 (4) When InAs layers are deposited, in layers, on a semiconductor layer having a lattice constant different from that of the InAs layer, there is a limit in the thickness of the InAs layer which can be deposited in layers without causing any defect. No InAs layer having a thickness required for designing an FET has been obtained because the upper limit of the film thickness, i.e., the critical film thickness is small. PA1 (5) A large stress is set up in the InAs layer due to a large difference between lattice constants of the InAs layer and a semiconductor layer which comes in contact with the InAs layer. This causes various problems such as thermal instability and large changes in properties with time and, therefore, the reliability of the resulting device is reduced. PA1 (6) The resulting devices do not exhibit functions sufficient for use as high frequency devices because of, for instance, a high parasitic capacitance generated between the substrate and the InAs layer. PA1 (7) A part of the material is very susceptible to oxidation. Therefore, the production method is quite complicated and the reliability of the device is insufficient. PA1 (8) A suitable Schottky junction or a non-ohmic junction such as a pn junction cannot be obtained because of the small bandgap energy of InAs.
For instance, Japanese Patent Application Laying-open No. 5439/1990 proposes the use of an InAs substrate. However, the InAs substrate is expensive and is not readily acceptable for industrial purposes. In addition, since an insulating substrate cannot be obtained at room temperature, the resulting device may have a parasitic capacitance between the InAs substrate and a channel layer, which capacity is an obstacle in obtaining good high speed characteristics.
On the other hand, there has also been known devices comprising an InAs thin film directly formed on a substrate whose lattice constant is quite different from that of the InAs film. For instance, Japanese Patent Application Laying-open No. 229438/1990 discloses a double heterojunction InAs-FET prepared by forming a GaAs buffer layer on a GaAs substrate through the molecular beam epitaxy (MBE) method, directly forming an InAs layer as a channel layer on the GaAs buffer layer, and then forming a GaAs layer on the InAs layer. Since an InAs layer is formed on a GaAs substrate having a lattice constant quite different from that of the InAs layer in this structure, the thickness of the InAs layer which gives an InAs thin film of good quality is limited to not more than about 209 .ANG.. This causes practical problems. For instance, it is an obstacle in designing a device having a high current-driving ability, or greatly restricts the degree of freedom in the design of devices.
As a method for relieving the lattice mismatching between a GaAs substrate and an InAs substrate, Japanese Patent Application Laying-open No. 5572/1985 proposes an InAs-FET which makes use of a stack of layers of GaSb and AlSb as a buffer layer. The difference between the lattice constants of GaSb and InAs is small and in the order of about 6%. However, it is not preferable to directly form an InAs thin film on the GaSb layer when producing an FET having an InAs layer serving as a channel layer, since, as shown in FIG. 1A, the upper edge of the valence band of a GaSb layer 102 is placed higher than the lower edge of the conduction band of an InAs layer 103. For this reason, an AlSb layer 104 is formed on the GaSb layer 102 as a current-barrier layer for electrically insulating the GaSb layer 102 from the InAs layer 103, and then the InAs layer 103 is formed on the AlSb layer 104 as shown in FIG. 1B. In this structure, however, the buffer layer is very complicated, and there is formed a parasitic capacitor which comprises the AlSb layer 104 serving as a dielectric film sandwiched between the GaSb layer 102 and the InAs layer 103 serving as electrodes as shown in FIG. 1C. Thus, this is not preferable as a structure for high speed devices. Moreover, since the difference in lattice constant between the AlSb layer 104 and the InAs layer 103 is as much as 1.25%, the critical film thickness of the InAs thin film 103 on the AlSb layer 104 cannot exceed 200 .ANG.. This is also an obstacle in forming devices capable of operating at a large electric current. In addition, the AlSb film 104 is very susceptible to oxidation. This property of the AlSb film makes the processes for, for instance, forming an active layer through the mesa etching technique complicated and the resulting device possibly shows property changes with time due to the oxidation. Therefore, the proposal is not practicable and further does not disclose any method for inhibiting such oxidation.
As another method for relieving the lattice mismatching between a GaAs substrate and an InAs substrate, IEEE ELECTRON DEVICE LETTERS, 1990, Vol. 11, No. 11, NOVEMBER discloses an InAs-FET in which the channel layer is composed of an InAs layer formed on a buffer layer consisting of a stack of layers of AlSb and Al.sub.0.5 Ga.sub.0.5 Sb. The structure of the InAs-FET is shown in FIG. 2A. The discrepancy between the lattice constants of Al.sub.0.5 Ga.sub.0.5 Sb and InAs is about 0.9%, and the critical film thickness of Al.sub.0.5 Ga.sub.0.5 Sb is not more than 300 .ANG.. This is also an obstacle in forming devices capable of operating at a high current. Moreover, in this example, an AlSb layer having a thickness of as thick as 2.8 .mu.m is used as a buffer layer positioned between a substrate and an Al.sub.0.5 Ga.sub.0.5 Sb layer, and the device has a complicated layer structure such that an AlSb layer of 60 .ANG. thickness is inserted between the InAs layer and the Al.sub.0.5 Ga.sub.0.5 Sb layer in order to increase the carrier concentration in the channel layer. Further, since the carriers in the channel layer are supplied from donor impurities which are unintentionally doped into the AlSb layer, or from the interface between the AlSb layer and the InAs layer, it is difficult to control the carrier concentration to agree with the design level of this FET. Thus, this technique has poor practicability since it has a problem in the industrial mass-production. FIG. 2B shows current-voltage characteristics of the InAs-FET fabricated according to the foregoing method. This device shows the pinch-off effect, but has poor linearity in the saturation region. In addition, the impact-ionization effect is conspicuous although it has a considerably long gate of 1.7 .mu.m. Therefore, this technique is impracticable as well.
There has been proposed an InAs-FET having a structure in which an InAs layer is sandwiched between AlGaAsSb layers whose lattice constant is approximately consistent with that of the InAs layer (Japanese Patent application Laying-open No. 144979/1985). The device of this proposal comprises on a semi-insulated InP substrate a buffer layer having a multi-layered structure of InGaAs in which the compositions and the lattice constants of the layers stepwise vary. This multi-layered structure is designed such that the lattice constants of the layers change stepwise from the lattice constant of the InP substrate to that of the InAs layer. Thereafter, a stack of films in which an InAs layer is sandwiched between AlGaAsSb layers is formed on the buffer layer. The AlGaAsSb layer is used as a barrier layer for confining conduction electrons within the InAs layer. The structure of the InAs-FET thus produced is very complicated and is not preferable from the viewpoint of production thereof. Moreover, the upper most InGaAs layer of the InGaAs multi-layered film serving as the buffer layer has properties quite similar to those of InAs and a bandgap approximately equal to that of InAs, and is a conductive material at ordinary temperature. This leads to the formation of a parasitic capacitor in which the AlGaAsSb layer serves as a dielectric film, and the InAs layer serving as the channel layer and the InGaAs layer serving as the buffer layer act as electrodes and, as a result, good high frequency characteristics cannot be obtained. In addition, since an ohmic contact is formed if a gate electrode directly comes in contact with an InAs layer, the structure must be designed such that this direct contact is prevented when an active region is formed by the mesa separation method. However, this reference does not disclose any such structure at all. In addition, the AlGaAsSb film is quite susceptible to oxidation when the content of Ga component is low and thus it is essential to take a proper measure for preventing oxidation of the AlGaAsSb film when an active region is formed by the mesa etching method or when a device has a structure in which the AlGaAsSb film on the InAs film is exposed. The proposal, however, does not disclose any means for preventing the oxidation.
As has been discussed above, although there have been many attempts which makes use of InAs having a high electron mobility as a channel layer of FETs, an FET structure that can be practically acceptable has not yet been proposed.